1. Field of the Invention
The present invention relates to a tristate output circuit.
2. Related art
At present, a MOS structure semiconductor device uses a tristate output circuit such as that shown in FIG. 3. The tristate output circuit comprises: a control unit 36 consisting of transmission gates 31 and 32, a control inverter 33 for the transmission gates 31 and 32, and a P-channel MOS transistor 34 and an N-channel MOS transistor 35 which respectively control the logic levels of output terminals out1 and out2 of the transmission gates 31 and 32; amplifier stages 37 and 38 in which CMOS inverters of the same number are cascaded and which respectively amplify signals from the output terminals out1 and out2 of the transmission gates 31 and 32; and an output stage 312 which has a P-channel MOS transistor 39 receiving at the gate an output of the amplifier stage 37, and an N-channel MOS transistor 310 receiving at the gate an output of the amplifier stage 38, and in which the drains of the transistors are connected to each other and the node is used as an output terminal 311. In each of the amplifier stages 37 and 38, plural CMOS inverters which respectively drive the subsequent stage and which have different drivabilities are cascaded in ascending order of drivability, and the states of the output terminals out1 and out2 are sequentially amplified to a level at which the P-channel MOS transistor 39 and the N-channel MOS transistor 310 that have high drivability can be driven. In this example, six CMOS inverters are cascaded.
In such a tristate output circuit, a first or second logic level, i.e., "H" or "L" is generated at the output terminal 311 in the following manner. The P-channel MOS transistor 34 and the N-channel MOS transistor 35 are turned OFF. A terminal 313 is set to be "H" so that the transmission gates 31 and 32 are opened. Signals which are in phase with each other are applied to input terminals in1 and in2 of the transmission gates 31 and 32, respectively. The signals at the input terminals in1 and in2 are amplified by the amplifier stages 37 and 38, and then applied to the P-channel MOS transistor 39 and the N-channel MOS transistor 310, respectively. These transistors are complementarily turned ON and OFF so that the output terminal 311 is set to be "H" or "L."
The terminal 313 is set to be "L" so that the transmission gates 31 and 32 are closed. The P-channel MOS transistor 34 and the N-channel MOS transistor 35 are turned ON. As a result, both the P-channel MOS transistor 39 and the N-channel MOS transistor 310 are turned OFF, and the output terminal 311 is set to be floating, thereby attaining a high impedance.
With respect to the P-channel MOS transistor 39 and the N-channel MOS transistor 310, as carriers, the former uses holes and the latter uses electrons. The mobility of a hole is inferior to that of an electron. In order to equalize the drivability of the P-channel MOS transistor to that of the N-channel MOS transistor, therefore, the size of the P-channel MOS transistor 39 must be larger than that of the N-channel MOS transistor 310 (for example, the gate is made larger). As a result, the gate capacitance of the P-channel MOS transistor 39 which is a load of a CMOS inverter 314 is larger than that of the N-channel MOS transistor 310 which is a load of a CMOS inverter 315. Therefore, the load of CMOS inverter 314 is larger than that of the CMOS inverter 315. When the two CMOS inverters are configured so as to have the same drivability, the response characteristics of the CMOS inverter 314 is inferior to those of the CMOS inverter 315. In order to drive the two CMOS inverters with the same response characteristics, therefore, the drivability of the CMOS inverter 314 which drives the P-channel MOS transistor 39 must be higher than that of the CMOS inverter 315 which drives the N-channel MOS transistor 310. In other words, the CMOS inverter 314 must be configured by MOS transistors which are larger in size than MOS transistors constituting the CMOS inverter 315.
Consequently, the CMOS inverters constituting the amplifier stages 37 and 38 have different drivabilities, or have different sizes.
A tristate output circuit is configured so that, when a clock signal consisting two states of "H" and "L" is to be generated as required, an output of an appropriate duty is obtained. In the tristate output circuit described above, however, the process of adjusting the duty is cumbersome because the CMOS inverters constituting the amplifier stages 37 and 38 are different in size from each other. Namely, when an output of a desired duty cannot be obtained after integration, the CMOS inverters of the amplifier stages 37 and 38 must be individually proved to check their outputs, thereby identifying a problematic portion. Furthermore, it is difficult to change the design because the CMOS inverters have different sizes.